PCB is mainly divided into

(1) Oxidized layer capacitance C1 between grid and channel;

(2) depletion layer capacitance C2 between substrate and channel;

(3) The overlapped capacitors C3 and C4 produced by the polysilicon gate and the source and drain;

(4) Junction capacitance C5 and C6 between the source/drain zone and the substrate.

Well, actually these MOS capacitors we just look at, after all we are not in the device business.

2. CMOS unit circuit and layout

In current technology, we mainly use CMOS (Complementary semiconductor, Complementary MOS) technology, which mainly combines two types of transistors, PMOS and NMOS, into a unit, which is called CMOS unit or inverter unit. Its structure integrates PMOS and NMOS on a single wafer at the same time and then grid-connected and leak-connected. The following is its structure diagram (about circuit symbols and functions will be explained later) :

IC design: CMOS devices and their circuits

In the figure above, NMOS are on the left and PMOS are on the right. A is the common-grid * input, Y is the common-leakage * output, VDD connects to the source of PMOS *, GND connects to GND.

The circuit symbol diagram below, the above CMOS inverter for the circuit symbol diagram is as follows:

IC design: CMOS devices and their circuits

Now let's take a look at how this CMOS inverter works to explain why CMOS technology is mainstream:

A When input signal A=1, PMOS is off and NMOS is on. The voltage of output signal Y is equivalent to that of GND, that is, Y=0. In this process, none of the power supply loops from VDD to GND is on-going, so theoretically there is no current flowing from VDD to GND, so the power consumption is 0.

B When the input signal A=0, PMOS is on, while NMOS is off, and the output signal Y=VDD=1. However, the power supply loop from VDD to GND is not on-going either, so theoretically there is no current flowing from VDD to GND, so the power consumption is also 0.

C Thus it can be concluded that, in theory, the inverter transmits the signal with no power consumption (well, we should say: power consumption * extremely low), which is why the CMOS process is used.

Let's look at the CMOS unit layout:

IC design: CMOS devices and their circuits

On the left is the circuit symbol of CMOS, and on the right is the layout (this layout will make do first). Let's take a look at this plate below:

* Metal (blue) connected to digital ground (Vss) from bottom up; The P-well region with white background and red dotted line border is for illustration. The lower green doped region forms NMOS, while the upper green doped region forms PMOS.

The green doped area is then distributed near the red polysilicon, and the polysilicon is then linked together (i.e. connecting the gates * of the PMOS and NMOS) and then led through the metal (that X represents the throughhole) as input Vi.

Then the source * of the lower NMOS is connected to the metal through the hole (green and blue are connected through X); The leakage * of NMOS and PMOS is connected to the same metal through a through-hole and then used as an output.

The source * of the PMOS is connected to the metal through a through-hole and then connected to a digital power supply.

* The more abstract (and nicer) graph looks like this:

IC design: CMOS devices and their circuits

That's it for the basics of layout. For the most detailed knowledge, check out the most detailed books.

3. CMOS gate circuit

①CMOS non-gate: The function of a CMOS unit above is the function of the non-gate, so the CMOS non-gate is the CMOS unit, also known as the inverter. The circuit structure is the circuit structure of the inverter.

(2) (two input) CMOS and NAND:

Directly on the drawing, the circuit symbol structure of CMOS and non gate is shown as follows:

IC design: CMOS devices and their circuits

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

③ The circuit symbol and working principle of (two-input) CMOS or NOR are as follows:

IC design: CMOS devices and their circuits

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

All digital logic circuits can be simplified by the above three kinds of circuits, that is to say, a circuit can be composed of NAND or NOR circuits. Let's take a look at their characteristics to deduce the characteristics of digital CMOS circuits.

Easy to know (let's take that as a conclusion anyway) :

The general structure of a reverse logic gate is as follows:

IC design: CMOS devices and their circuits

In addition, we also note that NMOS networks are in series when used with functions; In use or function, the NMOS network is in parallel. So you can remember that you need all of the NOMS to be together, you need only one of the NMOS to be together (or), and or or, depending on the string union structure of the NMOS.

Then design how many input NXXX gate, the number of NMOS string/parallel, and then PMOS is and/string can be.

4. CMOS power consumption representation

Power consumption refers to the energy consumed per unit time. Power consumption in digital systems mainly includes static power consumption and dynamic power consumption. We will discuss static power consumption and dynamic power consumption from the perspective of CMOS circuits.

CMOS static power consumption: Power consumption when the CMOS is not flipping/not working. When the CMOS is not working, that is, when the transistors are in the cut-off state, there is no current flowing from VDD to GND, but there is still some small current flowing from the source to the ground. This static current Idd is called the leakage current between the power source and the ground, which is related to the device (as to how the leakage current is caused, it will not be explained here). In junior high school, we learned that P=UI, so static power consumption can be expressed like this:

IC design: CMOS devices and their circuits

The dynamic power consumption of CMOS is the power consumed by capacitor charging and discharging when the signal changes between 0 and 1. As we know, not only CMOS devices have parasitic capacitors, but also capacitance between wires. CVdd^2 is the energy required to charge capacitor C to voltage Vdd. If the capacitor transforms f times per second (that is, the capacitor switches at a frequency of f, and in one second the capacitor charges f/2 times and discharges f/2 times), since the discharge does not require power from the supply, the dynamic power can be expressed as follows:

IC design: CMOS devices and their circuits

PS: The above list mainly lists some major power consumption. For example, in dynamic power consumption, in addition to the capacitor power consumption when flipping, there is also the short-circuit power consumption caused by the simultaneous on-off of PMOS and NMOS when the gate * signal is flipping.