General structure of inverting logic gates

IC design: CMOS devices and their circuits

In addition, we also note that NMOS networks are in series when used with functions; In use or function, the NMOS network is in parallel. So you can remember that you need all of the NOMS to be together, you need only one of the NMOS to be together (or), and or or, depending on the string union structure of the NMOS.

Then design how many input NXXX gate, the number of NMOS string/parallel, and then PMOS is and/string can be.

4. CMOS power consumption representation

Power consumption refers to the energy consumed per unit time. Power consumption in digital systems mainly includes static power consumption and dynamic power consumption. We will discuss static power consumption and dynamic power consumption from the perspective of CMOS circuits.

CMOS static power consumption: Power consumption when the CMOS is not flipping/not working. When the CMOS is not working, that is, when the transistors are in the cut-off state, there is no current flowing from VDD to GND, but there is still some small current flowing from the source to the ground. This static current Idd is called the leakage current between the power source and the ground, which is related to the device (as to how the leakage current is caused, it will not be explained here). In junior high school, we learned that P=UI, so static power consumption can be expressed like this:

IC design: CMOS devices and their circuits

The dynamic power consumption of CMOS is the power consumed by capacitor charging and discharging when the signal changes between 0 and 1. As we know, not only CMOS devices have parasitic capacitors, but also capacitance between wires. CVdd^2 is the energy required to charge capacitor C to voltage Vdd. If the capacitor transforms f times per second (that is, the capacitor switches at a frequency of f, and in one second the capacitor charges f/2 times and discharges f/2 times), since the discharge does not require power from the supply, the dynamic power can be expressed as follows:

IC design: CMOS devices and their circuits

PS: The above list mainly lists some major power consumption. For example, in dynamic power consumption, in addition to the capacitor power consumption when flipping, there is also the short-circuit power consumption caused by the simultaneous on-off of PMOS and NMOS when the gate * signal is flipping.

The above two types of power consumption are mainly considered. Maybe we'll talk more about that later when we document the low power design.

Small summary to recognize type switch | clamping overpressure device selection points:

Key points of ceramic gas discharge tube selection:

1. Voltage selection

Single use GDT: the arc voltage should be equal to the user's normal working voltage, and leave a certain margin.

Use with MOV: The DC breakdown voltage should be equal to the user's normal working voltage, and leave a certain margin.

2.GDT flow should be determined according to the lightning protection circuit design index, GDT flow should be greater than the lightning protection circuit design flow capacity.

Key points of semiconductor discharge tube selection;

1. The level of signal interface should be **Vs, with a certain margin.

2. Select TSS with different flow rates according to the level of surge to pass through.

3. The normal working current of the circuit cannot match the holding current of the TSS.

Key points of glass discharge tube selection:

1. The DC breakdown voltage should be equal to the user's normal operating voltage.

2. The flow rate of the glass discharge tube should be determined according to the design index of the lightning protection circuit. The flow rate of the glass discharge tube should be greater than the flow capacity of the lightning protection circuit design.

Key points of varistor/patch varistor selection:

1 pressure sensitive voltage to ** the user's normal working voltage, and leave a certain margin;

2. The flow rate of the varistor should be determined according to the design specifications of the lightning protection circuit. The flow rate of the varistor should be greater than the current capacity of the lightning protection circuit.

Key points of selection of transient suppression diode:

The breakdown voltage of S should be equal to the user's normal operating voltage, and leave a certain margin.

2. Use bidirectional or unidirectional TVS according to different application interfaces.

Dc power interface usually uses one-way TVS.

The AC power interface and communication interface generally use TVS in both directions.

3. TVS of different power should be selected according to the level of surge to be passed

Key points of ESD discharge diode selection:

1.ESD breakdown voltage to * the user's normal working voltage, and leave a certain margin.

2. Use bidirectional or unidirectional TVS according to different application interfaces.

The DC power interface is usually one-way.

The AC power interface and communication interface generally use TVS in both directions.

3. The higher the working frequency of the interface, the lower the capacity.

ESD discharge diode product selection ultimately or according to the specific needs of each customer to choose suitable ESD model. When selecting and improving solutions for customers, we must remember to follow the following two principles:

Vdrw≥ the operating voltage on the circuit

According to the application port, the protection level choose the chip varistor or diode, according to the transmission frequency choose the capacitance value, the higher the frequency, the lower the tolerance of the device, too large tolerance is easy to cause signal loss, therefore, must be according to their own needs to choose the appropriate ESD.