The analog signal wiring area is distributed on both sides of the PCB board

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3.2 Digital signal wiring should be placed in the digital signal wiring area as far as possible;

Analog signal routing should be placed in the analog signal routing area as far as possible;

(Isolation routing can be pre-placed to limit the routing to prevent routing out of the wiring area)

Digital and analog signals are routed vertically to reduce cross-coupling.

3.3 Confine analog signal routing to the analog signal routing area using isolated routing (usually ground).

a) In the analog area, isolated lines are routed around the analog signal wiring area on both sides of the PCB board, with a line width of 50-100mil;

b) Digital area isolation line around the digital signal wiring area on both sides of the PCB board, line width 50-100mil, one of the PCB board edge should be 200mil width.

3.4 Parallel bus interface signal Line width > 10mil(usually 12 to 15mil), such as /HCS, /HRD, /HWT, and /RESET.

3.5 Cable Width of analog signal > 10mil(usually 12-15mil), such as MICM, MICV, SPKV, VC, VREF, TXA1, TXA2, RXA, TELIN, TELOUT.

3.6 All other signals should be routed as wide as possible, line width > 5mil(generally 10mil), the wiring between components should be as short as possible (should be considered in advance when placing components).

3.7 Cable Width of the bypass capacitor to the corresponding IC > 25mil, and try to avoid using holes.

3.8 Signal lines passing through different areas (such as typical low speed control/status signals) should pass through the isolation ground at one (optional) or two points. If the wiring is located on only one side, the isolation ground can be moved to the other side of the PCB to skip the signal wiring and maintain continuity.

3.9 High-frequency signal cabling should use smooth arc or 45 degree Angle instead of 90 degree Angle.

3.10 High-frequency signal cables should be routed through holes.

3.11 Route all signals away from the crystal oscillator circuit.

3.12 For high-frequency signals, a single continuous route should be adopted to avoid the occurrence of several sections of cable extending from one point.

3.13 Leave at least 60mil of space around the punch (at all levels) in the DAA circuit.

3.14 Clear the grounding loop to prevent unexpected current feedback from affecting the power supply.

Step 4: Power supply

4.1 Determining Power Connections.

4.2 In the wiring area of digital signals, a 10uF electrolytic capacitor or tantalum capacitor and a 0.1uF porcelain capacitor are connected in parallel between the power supply/ground. Place one place at the power inlet and one place at the far end of the PCB board to prevent the noise caused by the peak pulse of the power supply.

4.3 For dual panels, in the same layer of electrical circuit, the p

4.4 Generally, route power cables first, and then signal cables.

5.ower supply with two side widths of 200mil is routed around the circuit. (The other side must be digitally processed.)

5.1 double panel, digital and analog components (except for DAA) around and did not use the area below to use digital or analog area filling, together, similar to the area of different levels of the different levels similar to area through multiple connected via: Modem DGND pin connected to digital area, AGND pin connected to analog ground area; The digital and analog areas are separated by a straight gap.

5.2 In four layers, digital and analog components (except DAA) are covered with digital and analog ground areas; Modem connected to DGND pin number area, AGND pin connected to analog ground area; The digital and analog areas are separated by a straight gap.

5.3 If EMI filter is required in the design, certain space should be reserved in the interface socket, and the majority of EMI devices (Bead/ capacitor) can be placed in this area; Unused areas are filled with land and, if there is a shielding enclosure, must be connected to it.

5.4 Separate power supplies for each function module. Function modules can be divided into: parallel bus interface, display, digital circuit (SRAM, EPROM, Modem) and DAA, etc. The power/ground of each function module can only be connected at the source point of power/ground.

5.5 For serial DTE modules, use decoupling capacitors to reduce power coupling, and the same can be done for telephone lines.

5.6 The earth wire is connected through a point, if possible, using Bead; Allow ground wires to be connected elsewhere if necessary to suppress EMI.

5.7 All ground cables should be as wide as possible, 25-50mil.

5.8 All IC power supply/ground capacitor cables should be as short as possible, and no holes should be used.

6. Crystal oscillator circuit

6.1 All the wiring connected to the Crystal oscillator input/output terminal (e.g. XTLI and XTLO) should be as short as possible to reduce noise interference and the influence of distributed capacitance on crystal. XTLO wiring should be as short as possible, and the bending Angle should not be less than 45 degrees. (Because XTLO is connected to the driver with fast rise time and high current)

6.2 There is no ground layer in the dual panel. Crystal capacitor ground wire should be connected to the device with a short wire as wide as possible

DGND pins close to crystal oscillator, and minimize overhole.

6.3 Ground the crystal oscillator housing if possible.

6.4 Connect a 100 Ohm resistor between the XTLO pin and the crystal/capacitor node.

6.5 Connect the ground of the crystal oscillator capacitor directly to the GND pins of the Modem. Do not use the ground wire area or ground wire routing to connect the GND pins of the capacitor and the Modem.

7. Design an independent Modem that uses the EIA/TIA-232 interface

7.1 Use a metal shell. If a plastic case is required, attach metal foil or spray conductive material inside to reduce EMI.

7.2 Place Choke of the same mode on each power cord.

7.3 Place the components together and close to the Connector of the EIA/TIA-232 interface.

7.4 Connect all EIA/TIA-232 devices to the power supply/ground separately from the power supply point. The source point of the power supply/ground should be the input end of the power supply on the board or the output end of the voltage regulator chip.

7.5 EIA/TIA-232 Cable Signal Ground to digital ground.

7.6 EIA/TIA-232 Cable shielding is not connected to the Modem shell in the following cases: Air connection; Bead received digitally; The EIA/TIA-232 cable is directly connected to the digital ground when a magnetic ring is placed near the enclosure of the Modem.

8. VC and VREF circuit capacitor wiring should be as short as possible, and located in the neutral area.

8.1 The connecting end of the 10uF VC electrolytic capacitor * and the 0.1uF VC capacitor is connected to the VC pin of the Modem (PIN24) through an independent cable.

VC 8.2 10 uF electrolytic capacitor negative * connection with VC 0.1 uF capacitance after end through the Bead with independent walk a line to the Modem AGND pin (PIN34).

8.3 The connecting end of the 10uF VREF electrolytic capacitor * and the 0.1uF VC capacitor is connected to the VREF pin (PIN25) of the Modem through an independent cable.

8.4 The connection end of the negative * of the 10uF VREF electrolytic capacitor and the 0.1uF VC capacitor is connected to the VC pin of the Modem (PIN24) through an independent cable; Note that it is independent of 8.1 Cabling.

VREF ------+--------+

The ┿ 10 u ┿ 0.1 u

VC ------+--------+

The ┿ 10 u ┿ 0.1 u

+ + -- -- -- -- -- -- -- -- -- -- -- -- -- ~ ~ ~ ~ ~ + AGND -

The Bead used should meet the following requirements:

At 100MHz, impedance =70W;

Rated current =200mA;

Larger resistance =0.5W.

9. The phone and Handset interfaces

9.1 Place the Choke at the junction of the Tip and Ring wire.

9.2 The decoupling method of telephone line is similar to that of power supply, which uses methods such as increasing inductance combination, Choke and capacitance. However, decoupling of telephone lines is more difficult than decoupling of power supplies and it is worth noting that the general practice is to reserve the location of these components for adjustment during performance /EMI test certification.

9.3 Place a high-voltage filter capacitor (0.001uF/1KV) between the Tip and Ring lines and the digital ground.