IC design: CMOS devices and their circuits

As shown in the upper left figure, the so-called source *, when applied with voltage, is equivalent to the source of electrons; The so-called leakage *, is equivalent to the leakage of the electron opening; And the grid in the middle, *, acts like a control switch: On the one hand, by controlling the high level voltage applied in the grid *, there is a channel between the source and drain, and the electrons flow from the source to the drain through the channel, and the direction of the current is from the drain to the source, so as to conduct electricity, that is, when the "switch" is opened (due to the formation of N channel, that is, electronic conduction, so it becomes N-type CMOS).

 On the other hand, a low level voltage is applied to the gate by the control, so that the channel is off, so that the source and drain are off, that is, when the "switch" is off. This is the structure and workflow of NMOS. (PMOS work in the opposite way: turn on by controlling the low level voltage applied to the gate, and turn off the channel by controlling the high level voltage applied to the gate.)

Note: When the voltage of the gate * reaches a certain value, the channel will be formed. The voltage when the channel is formed is called the threshold voltage (Vth)

② Let's take a look at the I-V characteristic curve (note the two names, one is transfer characteristic curve, one is output characteristic curve) :

IC design: CMOS devices and their circuits

In * we know that for NMOS, the source (S) is grounded, the drain *(D) is connected to the digital power supply, at work, the general Vds is constant, and then according to the voltage on the gate(G) to determine whether the channel is open. When working, the value of Vg (that is, the voltage value of the input signal) is a fixed value, which is either high level (may fluctuate) or low level. From here, we also know that when NMOS works, there is current flowing from the power supply (VDD) to the ground (that is, from D to S). When the power supply voltage is constant, This current follows the voltage across the gate.

③ Then let's take a look at the internal self-formed capacitance (parasitic capacitance) of MOS, as shown in the figure below:

IC design: CMOS devices and their circuits

It is mainly divided into:

(1) Oxidized layer capacitance C1 between grid and channel;

(2) depletion layer capacitance C2 between substrate and channel;

(3) The overlapped capacitors C3 and C4 produced by the polysilicon gate and the source and drain;

(4) Junction capacitance C5 and C6 between the source/drain zone and the substrate.

Well, actually these MOS capacitors we just look at, after all we are not in the device business.

2. CMOS unit circuit and layout

In current technology, we mainly use CMOS (Complementary semiconductor, Complementary MOS) technology, which mainly combines two types of transistors, PMOS and NMOS, into a unit, which is called CMOS unit or inverter unit. Its structure integrates PMOS and NMOS on a single wafer at the same time and then grid-connected and leak-connected. The following is its structure diagram (about circuit symbols and functions will be explained later) :

IC design: CMOS devices and their circuits

In the figure above, NMOS are on the left and PMOS are on the right. A is the common-grid * input, Y is the common-leakage * output, VDD connects to the source of PMOS *, GND connects to GND.

The circuit symbol diagram below, the above CMOS inverter for the circuit symbol diagram is as follows:

IC design: CMOS devices and their circuits

Now let's take a look at how this CMOS inverter works to explain why CMOS technology is mainstream:

A When input signal A=1, PMOS is off and NMOS is on. The voltage of output signal Y is equivalent to that of GND, that is, Y=0. In this process, none of the power supply loops from VDD to GND is on-going, so theoretically there is no current flowing from VDD to GND, so the power consumption is 0.

B When the input signal A=0, PMOS is on, while NMOS is off, and the output signal Y=VDD=1. However, the power supply loop from VDD to GND is not on-going either, so theoretically there is no current flowing from VDD to GND, so the power consumption is also 0.

C Thus it can be concluded that, in theory, the inverter transmits the signal with no power consumption (well, we should say: power consumption * extremely low), which is why the CMOS process is used.

Let's look at the CMOS unit layout:

IC design: CMOS devices and their circuits

On the left is the circuit symbol of CMOS, and on the right is the layout (this layout will make do first). Let's take a look at this plate below:

* Metal (blue) connected to digital ground (Vss) from bottom up; The P-well region with white background and red dotted line border is for illustration. The lower green doped region forms NMOS, while the upper green doped region forms PMOS.

The green doped area is then distributed near the red polysilicon, and the polysilicon is then linked together (i.e. connecting the gates * of the PMOS and NMOS) and then led through the metal (that X represents the throughhole) as input Vi.

Then the source * of the lower NMOS is connected to the metal through the hole (green and blue are connected through X); The leakage * of NMOS and PMOS is connected to the same metal through a through-hole and then used as an output.

The source of the PMOS is connected to the metal through a through-hole and then connected to a digital power supply.

* The more abstract (and nicer) graph looks like this:

IC design: CMOS devices and their circuits

That's it for the basics of layout. For the most detailed knowledge, check out the most detailed books.

3. CMOS gate circuit

①CMOS non-gate: The function of a CMOS unit above is the function of the non-gate, so the CMOS non-gate is the CMOS unit, also known as the inverter. The circuit structure is the circuit structure of the inverter.

(2) (two input) CMOS and NAND:

Directly on the drawing, the circuit symbol structure of CMOS and non gate is shown as follows:

IC design: CMOS devices and their circuits

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

③ The circuit symbol and working principle of (two-input) CMOS or NOR are as follows:

IC design: CMOS devices and their circuits

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

All digital logic circuits can be simplified by the above three kinds of circuits, that is to say, a circuit can be composed of NAND or NOR circuits. Let's take a look at their characteristics to deduce the characteristics of digital CMOS circuits.

Easy to know (let's take that as a conclusion anyway) :

The general structure of a reverse logic gate is as follows:

IC design: CMOS devices and their circuits

In addition, we also note that NMOS networks are in series when used with functions; In use or function, the NMOS network is in parallel. So you can remember that you need all of the NOMS to be together, you need only one of the NMOS to be together (or), and or or, depending on the string union structure of the NMOS.

Then design how many input NXXX gate, the number of NMOS string/parallel, and then PMOS is and/string can be.