An example of software and hardware design for a multi-CPU parallel computer system

The parallel computer technology of multi-CPU improves the computing speed of the system to a great extent, breaking through the limit of the processing speed of single CPU. The design of single board computer with multiple cpus can reduce the volume of computer system, reduce the development cost and reduce the development cycle of the system.

Hardware design of multiprocessor parallel computer system

The multi-processor parallel computer system is a system model of parallel structure. Each processor needs to have its own local memory to store its own application program and can do independent high-speed parallel computation. At the same time, the system needs the interconnection network with high speed communication, which can distribute parallel data blocks in the local memory of each processor at high speed, so as to improve the efficiency of the parallel system. The computer architecture design can be configured with a loosely-coupled asymmetric processor with shared memory (dual-port RAM) interconnection. The system structure is shown in Figure 1. Each processor in the figure has its own high-speed local memory, which can be used for high-speed independent parallel calculation. Each processor is interconnected by dual-port memory to form a high-speed star communication network. Therefore, the loosely-coupled multi-CPU parallel computer with dual-port memory interconnection has the following advantages:

⑴ Communication bandwidth. CPU access dual-port memory can be byte/word/double-word length, high data read/write speed.

The structure is simple. The processor is directly connected to the dual-port memory, and no other interface circuit is needed, which can realize reliable bidirectional information transmission.

⑶ It has clipability. The number of processors can be increased or decreased as needed.

(4) Strong expansibility. The system architecture can be adapted to various processors.

In the multi-processor computer model, the CPU can be Intel x86 series, PowerPC series, ARM series and other processors. The Boot Processor (master Processor) manages the system by coordinating the work of the Application processors (slave processors) while initializing the shared memory. To improve the system's power-on efficiency, each processor needs to come with its own fash electronic disk to store programs, and each processor can plug in devices (such as networking, keyboards, etc.).

Ii. Software design of multi-processor parallel computer

In order to improve the execution efficiency of the processor, the general computer system uses real-time multi-task operating system. This paper discusses the software design method of multi-CPU parallel computer based on embedded VxWorks operating system.

1. Shared memory network

 In the VxWorks operating system, multiple cpus communicate with each other using Shared-Memory backplanetWork. This technology uses virtual network to manage shared storage devices. The shared memory network driver allows the communication between multiple processors to adopt the network form, and the usage specification conforms to the BSD4.4 compatibility mode. Shared memory can reside on the CPU motherboard or on a separate memory board.

BP represents the Boot Processor (master Processor) and AP represents the Application Processor (slave processor). The master processor is configured with host route 200.200.200.0. The slave processor can communicate with the external network through the master processor. The main processor must have two network interfaces, one for communicating with the external network (such as VxWorks development host Vx-Host), and the IP address is set to 90.0.0.10. The other is a virtual shared memory network, used to communicate with slave processors. The network IP addresses configured for the slave processor are 200.200.200.1, 200.200.2, and 200.200.200.3. When debugging the program, the main processor first initializes the shared memory network (including setting the memory address), and downloads its VxWorks image from the development host. Then, the dispatch slave processor (AP) downloads the VxWorks image required by the slave processor from the development host VxHost using IP address 90.0.0.10, and runs the operating system. All debugging of the slave is carried out through the master processor.

The shared memory network is a VxWorks module and must be selected from tornado's options for use. Each processor has its own boorom or VxWoks image, which runs its own operating system and communicates with each other through shared memory when needed.

2, shared memory network master equipment

 In a multiprocessor system, one processor acts as the master device. The functions of a shared-memory network Master in the system are explained as follows:

(1) Initialize the shared memory area and the shared memory hook (anchor);

⑵ Maintaining the shared memory network heartbeat;

(3) As a gateway for communication between other processors and the external network;

(4) Allocate shared storage areas.