Six Methods of FPGA Timing Constraints in PCB Design

The more you understand the implementation method of your own PCB design, the more you understand the timing requirements of your own PCB design, the more you understand the resource distribution and structure of the target PCB device, and the more you understand the effect of EDA tool execution constraints, the clearer the timing constraint target of PCB design, and correspondingly, the more controllable the timing convergence process of the design.

The following summarizes several methods for timing constraints. The order of easy to difficult is as follows:

0. Core frequency constraint

This is the most basic, so the label is 0

1. Core frequency constraint+timing exception constraint

Timing exception constraints include FalsePath, MulticyclePath, MaxDelay, and MinDelay But this is not the most complete temporal constraint. If there are only these constraints, it shows that the designer's thinking is still limited to the FPGA chip.

2. Core frequency constraint+timing exception constraint+I/O constraint

I/O constraints include pin assignment position, idle pin drive mode, external wiring delay (InputDelay, OutputDelay), pull-up and pull-down resistance, drive current strength, etc. The timing constraint after I/O constraint is added is the complete timing constraint. As a component on PCB, FPGA is a part of the timing convergence of the whole PCB system. As a part of PCB design, FPGA requires PCB design engineers to read and analyze its I/O Timing Diagram just like all COTS devices. FPGA differs from COTS devices in that its I/O timing can be adjusted within a certain range in the late design stage; Nevertheless, it is better to give full consideration in the early stage of PCB design and include it in the design document.

Just because the I/O timing of FPGA will change during the design, accurately constraining it is an important factor to ensure the stability and controllability of the design. After the recompilation of FPGA, many problems of unstable operation of FPGA external devices may be caused by this.

3. Core frequency constraint+timing exception constraint+I/O constraint+Post fit Netlist

The process of introducing Post fit Netlist starts with a successful timing convergence result, and fixes the layout position and routing result (Netlist) of a specific set of logic (Design Partition) implemented on FPGA to ensure that this layout and routing result can be reproduced in the new compilation. Accordingly, the timing convergence result of this set of logic is also guaranteed. The process of retaining the results of the last compilation in this part is incremental compilation. You can set the type of netlist to be retained and the degree of retention, not just limited to Post fit Netlist, so as to obtain the corresponding retention strength and optimization effect. Thanks to the strong support of EDA tools, although it is a fine-grained constraint accurate to the gate level, designers only need to carry out a series of setting operations, and do not need to care about the specific information of layout and routing. Because there are too many constraints accurate to the gate level, which cannot be saved in the qsf file, the retained netlist can be output to a separate file qxp in the form of partial Netlist, and incremental compilation can be completed together with the rough configuration information in the qsf file.

4. Core frequency constraint+timing exception constraint+I/O constraint+LogicLock

LogicLock is a layout constraint on the bottom layer of FPGA devices. LogicLock constraints are coarse grained, which only specify the layout location and size (LogicLock Regions) that can be adjusted for top-level modules or submodules. A successful LogicLock requires the designer to predict the possible timing convergence goal, consider the impact of the location relationship between specific logic resources (pins, memory, DSP) and LogicLock Region on timing, and refer to the results of the successful timing convergence last time. The process of balancing and planning the underlying physical layout of FPGA is FloorPlanNing LogicLock gives the designer more control over the layout location and scope, which can effectively transfer the designer's design intent to EDA tools, and avoid EDA tools blindly optimizing non critical paths due to lack of layout priority information. Since the change of the layout position of the module in each compilation is limited to the optimal fixed range, the reproducibility of the timing convergence results is higher. Because of its coarse granularity, LogicLock does not have much constraint information, which can be retained in the qsf file.

5. Core frequency constraint+timing exception constraint+I/O constraint+register layout constraint

The register layout constraint is a fine-grained layout constraint accurate to the register or LE level. PCB designers can obtain reliable timing convergence results by exerting precise control on the design. It is a huge project to manually constrain the placement of each register in the design and ensure the timing convergence, which indicates that the designer can fully control the physical implementation of the design. This is an ideal goal, which cannot be completed in a limited time. The usual approach is that the designer restricts the register layout of the design part and obtains the timing convergence information by actually running the layout and routing tool, and approximates the expected timing target through several iterations.

I have seen such a design: each register of a sub module has a specific layout position constraint. The timing convergence of the module is guaranteed in each recompilation. After analysis, the design and constraints of this sub module were initially carried out in the schematic diagram. After achieving the goal of timing convergence, the design was converted to HDL language description, and the corresponding constraints were also saved in the configuration file.

6. Core frequency constraint+timing exception constraint+I/O constraint+specific path delay constraint

Good timing constraints should be "guided" rather than "mandatory". By giving the timing delay range of the critical path in the design, the concrete and subtle work is left to EDA tools to realize freely within the limited range of the constraint. This is also an ideal goal. The designer needs to know every time sequence path well. The designer needs to distinguish which paths can be converged through core frequency and simple time sequence exception constraints, which paths must be formulated with MaxDelay and MinDelay. Neither of them can be omitted, and it also needs the strong support of EDA tool "understanding". Setting path delay constraints is to set layout and routing constraints indirectly, but it is more flexible and accurate than the methods in 3, 4 and 5 above. The essence of temporal constraints is to achieve temporal convergence through temporal constraints rather than explicit layout and net list constraints.

I remember someone said, "Good timing is designed, not constrained." I always use this sentence as a guide for my own logic design and timing constraints. Good constraints must be based on good design. Without good design, it is meaningless to make great efforts on constraints. However, the advantages and disadvantages of the design can also be checked through correct constraints. The PCB timing analysis report can be used to check out the inadvertent timing considerations in the design and modify them. The goal of improving the design can also be achieved through several "analysis - modification - analysis" iterations. It should be said that design is the basis of constraints, and constraints are the guarantee of design. The two are complementary